-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sun Oct 19 21:48:12 2025
-- Host        : wwws12 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               d:/FPGA_Proj/pynq_test_1019/pynq_test_1019.gen/sources_1/bd/linux_board/ip/linux_board_board_test_0_0/linux_board_board_test_0_0_sim_netlist.vhdl
-- Design      : linux_board_board_test_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity linux_board_board_test_0_0_board_test is
  port (
    led : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rgbled0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rgbled1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
    sys_clk : in STD_LOGIC;
    sw : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of linux_board_board_test_0_0_board_test : entity is "board_test";
end linux_board_board_test_0_0_board_test;

architecture STRUCTURE of linux_board_board_test_0_0_board_test is
  signal blink_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \blink_reg0__0\ : STD_LOGIC;
  signal \blink_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \blink_reg[1]_i_1_n_0\ : STD_LOGIC;
  signal \blink_reg[2]_i_1_n_0\ : STD_LOGIC;
  signal \blink_reg[3]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt[0][0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt[0][0]_i_3_n_0\ : STD_LOGIC;
  signal \btn_cnt[1][0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt[1][0]_i_3_n_0\ : STD_LOGIC;
  signal \btn_cnt[2][0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt[2][0]_i_3_n_0\ : STD_LOGIC;
  signal \btn_cnt[3][0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt[3][0]_i_3_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[0][0]_i_2_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[0][12]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[0][16]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[0][16]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[0][16]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[0][16]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[0][16]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[0][4]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[0][8]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[0]_0\ : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \btn_cnt_reg[1][0]_i_2_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[1][0]_i_2_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[1][12]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[1][16]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[1][16]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[1][16]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[1][16]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[1][16]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[1][4]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[1][8]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[1]_1\ : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \btn_cnt_reg[2][0]_i_2_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[2][0]_i_2_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[2][12]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[2][16]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[2][16]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[2][16]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[2][16]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[2][16]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[2][4]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[2][8]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[2]_2\ : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \btn_cnt_reg[3][0]_i_2_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[3][0]_i_2_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[3][12]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[3][16]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[3][16]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[3][16]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[3][16]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[3][16]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[3][4]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_0\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_1\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_2\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_3\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_4\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_5\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_6\ : STD_LOGIC;
  signal \btn_cnt_reg[3][8]_i_1_n_7\ : STD_LOGIC;
  signal \btn_cnt_reg[3]_3\ : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \btn_complete[0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_complete[1]_i_1_n_0\ : STD_LOGIC;
  signal \btn_complete[2]_i_1_n_0\ : STD_LOGIC;
  signal \btn_complete[3]_i_1_n_0\ : STD_LOGIC;
  signal \btn_complete_reg_n_0_[0]\ : STD_LOGIC;
  signal \btn_complete_reg_n_0_[1]\ : STD_LOGIC;
  signal \btn_pressed[0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_pressed[1]_i_1_n_0\ : STD_LOGIC;
  signal \btn_pressed[2]_i_1_n_0\ : STD_LOGIC;
  signal \btn_pressed[3]_i_1_n_0\ : STD_LOGIC;
  signal \btn_pressed_reg_n_0_[0]\ : STD_LOGIC;
  signal \btn_prev_reg_n_0_[0]\ : STD_LOGIC;
  signal \btn_stable[0]_i_1_n_0\ : STD_LOGIC;
  signal \btn_stable[0]_i_2_n_0\ : STD_LOGIC;
  signal \btn_stable[0]_i_3_n_0\ : STD_LOGIC;
  signal \btn_stable[0]_i_4_n_0\ : STD_LOGIC;
  signal \btn_stable[0]_i_5_n_0\ : STD_LOGIC;
  signal \btn_stable[0]_i_6_n_0\ : STD_LOGIC;
  signal \btn_stable[1]_i_1_n_0\ : STD_LOGIC;
  signal \btn_stable[1]_i_2_n_0\ : STD_LOGIC;
  signal \btn_stable[1]_i_3_n_0\ : STD_LOGIC;
  signal \btn_stable[1]_i_4_n_0\ : STD_LOGIC;
  signal \btn_stable[1]_i_5_n_0\ : STD_LOGIC;
  signal \btn_stable[1]_i_6_n_0\ : STD_LOGIC;
  signal \btn_stable[2]_i_1_n_0\ : STD_LOGIC;
  signal \btn_stable[2]_i_2_n_0\ : STD_LOGIC;
  signal \btn_stable[2]_i_3_n_0\ : STD_LOGIC;
  signal \btn_stable[2]_i_4_n_0\ : STD_LOGIC;
  signal \btn_stable[2]_i_5_n_0\ : STD_LOGIC;
  signal \btn_stable[2]_i_6_n_0\ : STD_LOGIC;
  signal \btn_stable[3]_i_1_n_0\ : STD_LOGIC;
  signal \btn_stable[3]_i_2_n_0\ : STD_LOGIC;
  signal \btn_stable[3]_i_3_n_0\ : STD_LOGIC;
  signal \btn_stable[3]_i_4_n_0\ : STD_LOGIC;
  signal \btn_stable[3]_i_5_n_0\ : STD_LOGIC;
  signal \btn_stable[3]_i_6_n_0\ : STD_LOGIC;
  signal \btn_stable_reg_n_0_[0]\ : STD_LOGIC;
  signal \btn_stable_reg_n_0_[1]\ : STD_LOGIC;
  signal \color_idx[0]_i_1_n_0\ : STD_LOGIC;
  signal \color_idx[1]_i_1_n_0\ : STD_LOGIC;
  signal \color_idx[2]_i_1_n_0\ : STD_LOGIC;
  signal \color_idx_reg_n_0_[0]\ : STD_LOGIC;
  signal \color_idx_reg_n_0_[1]\ : STD_LOGIC;
  signal \color_idx_reg_n_0_[2]\ : STD_LOGIC;
  signal \led_mode[0]_i_1_n_0\ : STD_LOGIC;
  signal \led_mode[1]_i_1_n_0\ : STD_LOGIC;
  signal \led_mode_reg_n_0_[0]\ : STD_LOGIC;
  signal \led_mode_reg_n_0_[1]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in33_in : STD_LOGIC;
  signal p_0_in36_in : STD_LOGIC;
  signal p_0_in39_in : STD_LOGIC;
  signal p_0_in4_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_2_in20_in : STD_LOGIC;
  signal p_2_in24_in : STD_LOGIC;
  signal p_2_in28_in : STD_LOGIC;
  signal sec_pulse : STD_LOGIC;
  signal sec_pulse_i_10_n_0 : STD_LOGIC;
  signal sec_pulse_i_11_n_0 : STD_LOGIC;
  signal sec_pulse_i_1_n_0 : STD_LOGIC;
  signal sec_pulse_i_2_n_0 : STD_LOGIC;
  signal sec_pulse_i_3_n_0 : STD_LOGIC;
  signal sec_pulse_i_4_n_0 : STD_LOGIC;
  signal sec_pulse_i_5_n_0 : STD_LOGIC;
  signal sec_pulse_i_6_n_0 : STD_LOGIC;
  signal sec_pulse_i_7_n_0 : STD_LOGIC;
  signal sec_pulse_i_8_n_0 : STD_LOGIC;
  signal sec_pulse_i_9_n_0 : STD_LOGIC;
  signal shift_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \shift_reg0__0\ : STD_LOGIC;
  signal \time_cnt[0]_i_2_n_0\ : STD_LOGIC;
  signal time_cnt_reg : STD_LOGIC_VECTOR ( 26 downto 0 );
  signal \time_cnt_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \time_cnt_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[24]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[24]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[24]_i_1_n_7\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \time_cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \NLW_btn_cnt_reg[0][16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_btn_cnt_reg[0][16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_btn_cnt_reg[1][16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_btn_cnt_reg[1][16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_btn_cnt_reg[2][16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_btn_cnt_reg[2][16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_btn_cnt_reg[3][16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_btn_cnt_reg[3][16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_time_cnt_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_time_cnt_reg[24]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \blink_reg[0]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \blink_reg[1]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \blink_reg[2]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \blink_reg[3]_i_1\ : label is "soft_lutpair9";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[0][0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[0][12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[0][16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[0][4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[0][8]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[1][0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[1][12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[1][16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[1][4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[1][8]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[2][0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[2][12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[2][16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[2][4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[2][8]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[3][0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[3][12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[3][16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[3][4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \btn_cnt_reg[3][8]_i_1\ : label is 11;
  attribute SOFT_HLUTNM of \btn_complete[0]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \btn_complete[1]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \btn_complete[2]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \btn_complete[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \btn_pressed[0]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \btn_pressed[1]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \btn_pressed[2]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \btn_pressed[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \color_idx[0]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \color_idx[1]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \color_idx[2]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \led[0]_INST_0\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \led[1]_INST_0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \led[2]_INST_0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \led[3]_INST_0\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \rgbled0[0]_INST_0\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \rgbled0[1]_INST_0\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \rgbled0[2]_INST_0\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \rgbled1[0]_INST_0\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \rgbled1[1]_INST_0\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of sec_pulse_i_11 : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of sec_pulse_i_7 : label is "soft_lutpair12";
  attribute ADDER_THRESHOLD of \time_cnt_reg[0]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_cnt_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_cnt_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_cnt_reg[20]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_cnt_reg[24]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_cnt_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \time_cnt_reg[8]_i_1\ : label is 11;
begin
blink_reg0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => sec_pulse,
      I1 => \led_mode_reg_n_0_[1]\,
      I2 => \led_mode_reg_n_0_[0]\,
      O => \blink_reg0__0\
    );
\blink_reg[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => blink_reg(0),
      O => \blink_reg[0]_i_1_n_0\
    );
\blink_reg[1]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => blink_reg(1),
      O => \blink_reg[1]_i_1_n_0\
    );
\blink_reg[2]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => blink_reg(2),
      O => \blink_reg[2]_i_1_n_0\
    );
\blink_reg[3]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => blink_reg(3),
      O => \blink_reg[3]_i_1_n_0\
    );
\blink_reg_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => \blink_reg0__0\,
      D => \blink_reg[0]_i_1_n_0\,
      Q => blink_reg(0),
      S => p_1_in
    );
\blink_reg_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => \blink_reg0__0\,
      D => \blink_reg[1]_i_1_n_0\,
      Q => blink_reg(1),
      S => p_1_in
    );
\blink_reg_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => \blink_reg0__0\,
      D => \blink_reg[2]_i_1_n_0\,
      Q => blink_reg(2),
      S => p_1_in
    );
\blink_reg_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => \blink_reg0__0\,
      D => \blink_reg[3]_i_1_n_0\,
      Q => blink_reg(3),
      S => p_1_in
    );
\btn_cnt[0][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF800F800FFFF"
    )
        port map (
      I0 => \btn_stable[0]_i_2_n_0\,
      I1 => \btn_cnt_reg[0]_0\(13),
      I2 => \btn_cnt_reg[0]_0\(14),
      I3 => \btn_stable[0]_i_3_n_0\,
      I4 => btn(0),
      I5 => \btn_stable_reg_n_0_[0]\,
      O => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt[0][0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \btn_cnt_reg[0]_0\(0),
      O => \btn_cnt[0][0]_i_3_n_0\
    );
\btn_cnt[1][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF800F800FFFF"
    )
        port map (
      I0 => \btn_stable[1]_i_2_n_0\,
      I1 => \btn_cnt_reg[1]_1\(13),
      I2 => \btn_cnt_reg[1]_1\(14),
      I3 => \btn_stable[1]_i_3_n_0\,
      I4 => btn(1),
      I5 => \btn_stable_reg_n_0_[1]\,
      O => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt[1][0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \btn_cnt_reg[1]_1\(0),
      O => \btn_cnt[1][0]_i_3_n_0\
    );
\btn_cnt[2][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF800F800FFFF"
    )
        port map (
      I0 => \btn_stable[2]_i_2_n_0\,
      I1 => \btn_cnt_reg[2]_2\(13),
      I2 => \btn_cnt_reg[2]_2\(14),
      I3 => \btn_stable[2]_i_3_n_0\,
      I4 => btn(2),
      I5 => p_0_in1_in,
      O => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt[2][0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \btn_cnt_reg[2]_2\(0),
      O => \btn_cnt[2][0]_i_3_n_0\
    );
\btn_cnt[3][0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF800F800FFFF"
    )
        port map (
      I0 => \btn_stable[3]_i_2_n_0\,
      I1 => \btn_cnt_reg[3]_3\(13),
      I2 => \btn_cnt_reg[3]_3\(14),
      I3 => \btn_stable[3]_i_3_n_0\,
      I4 => btn(3),
      I5 => p_0_in4_in,
      O => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt[3][0]_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \btn_cnt_reg[3]_3\(0),
      O => \btn_cnt[3][0]_i_3_n_0\
    );
\btn_cnt_reg[0][0]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][0]_i_2_n_7\,
      Q => \btn_cnt_reg[0]_0\(0),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \btn_cnt_reg[0][0]_i_2_n_0\,
      CO(2) => \btn_cnt_reg[0][0]_i_2_n_1\,
      CO(1) => \btn_cnt_reg[0][0]_i_2_n_2\,
      CO(0) => \btn_cnt_reg[0][0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \btn_cnt_reg[0][0]_i_2_n_4\,
      O(2) => \btn_cnt_reg[0][0]_i_2_n_5\,
      O(1) => \btn_cnt_reg[0][0]_i_2_n_6\,
      O(0) => \btn_cnt_reg[0][0]_i_2_n_7\,
      S(3 downto 1) => \btn_cnt_reg[0]_0\(3 downto 1),
      S(0) => \btn_cnt[0][0]_i_3_n_0\
    );
\btn_cnt_reg[0][10]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][8]_i_1_n_5\,
      Q => \btn_cnt_reg[0]_0\(10),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][11]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][8]_i_1_n_4\,
      Q => \btn_cnt_reg[0]_0\(11),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][12]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][12]_i_1_n_7\,
      Q => \btn_cnt_reg[0]_0\(12),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[0][8]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[0][12]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[0][12]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[0][12]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[0][12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[0][12]_i_1_n_4\,
      O(2) => \btn_cnt_reg[0][12]_i_1_n_5\,
      O(1) => \btn_cnt_reg[0][12]_i_1_n_6\,
      O(0) => \btn_cnt_reg[0][12]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[0]_0\(15 downto 12)
    );
\btn_cnt_reg[0][13]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][12]_i_1_n_6\,
      Q => \btn_cnt_reg[0]_0\(13),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][14]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][12]_i_1_n_5\,
      Q => \btn_cnt_reg[0]_0\(14),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][15]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][12]_i_1_n_4\,
      Q => \btn_cnt_reg[0]_0\(15),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][16]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][16]_i_1_n_7\,
      Q => \btn_cnt_reg[0]_0\(16),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[0][12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_btn_cnt_reg[0][16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \btn_cnt_reg[0][16]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[0][16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_btn_cnt_reg[0][16]_i_1_O_UNCONNECTED\(3),
      O(2) => \btn_cnt_reg[0][16]_i_1_n_5\,
      O(1) => \btn_cnt_reg[0][16]_i_1_n_6\,
      O(0) => \btn_cnt_reg[0][16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => \btn_cnt_reg[0]_0\(18 downto 16)
    );
\btn_cnt_reg[0][17]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][16]_i_1_n_6\,
      Q => \btn_cnt_reg[0]_0\(17),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][18]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][16]_i_1_n_5\,
      Q => \btn_cnt_reg[0]_0\(18),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][1]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][0]_i_2_n_6\,
      Q => \btn_cnt_reg[0]_0\(1),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][2]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][0]_i_2_n_5\,
      Q => \btn_cnt_reg[0]_0\(2),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][3]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][0]_i_2_n_4\,
      Q => \btn_cnt_reg[0]_0\(3),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][4]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][4]_i_1_n_7\,
      Q => \btn_cnt_reg[0]_0\(4),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[0][0]_i_2_n_0\,
      CO(3) => \btn_cnt_reg[0][4]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[0][4]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[0][4]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[0][4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[0][4]_i_1_n_4\,
      O(2) => \btn_cnt_reg[0][4]_i_1_n_5\,
      O(1) => \btn_cnt_reg[0][4]_i_1_n_6\,
      O(0) => \btn_cnt_reg[0][4]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[0]_0\(7 downto 4)
    );
\btn_cnt_reg[0][5]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][4]_i_1_n_6\,
      Q => \btn_cnt_reg[0]_0\(5),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][6]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][4]_i_1_n_5\,
      Q => \btn_cnt_reg[0]_0\(6),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][7]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][4]_i_1_n_4\,
      Q => \btn_cnt_reg[0]_0\(7),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][8]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][8]_i_1_n_7\,
      Q => \btn_cnt_reg[0]_0\(8),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[0][8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[0][4]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[0][8]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[0][8]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[0][8]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[0][8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[0][8]_i_1_n_4\,
      O(2) => \btn_cnt_reg[0][8]_i_1_n_5\,
      O(1) => \btn_cnt_reg[0][8]_i_1_n_6\,
      O(0) => \btn_cnt_reg[0][8]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[0]_0\(11 downto 8)
    );
\btn_cnt_reg[0][9]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[0][8]_i_1_n_6\,
      Q => \btn_cnt_reg[0]_0\(9),
      R => \btn_cnt[0][0]_i_1_n_0\
    );
\btn_cnt_reg[1][0]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][0]_i_2_n_7\,
      Q => \btn_cnt_reg[1]_1\(0),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \btn_cnt_reg[1][0]_i_2_n_0\,
      CO(2) => \btn_cnt_reg[1][0]_i_2_n_1\,
      CO(1) => \btn_cnt_reg[1][0]_i_2_n_2\,
      CO(0) => \btn_cnt_reg[1][0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \btn_cnt_reg[1][0]_i_2_n_4\,
      O(2) => \btn_cnt_reg[1][0]_i_2_n_5\,
      O(1) => \btn_cnt_reg[1][0]_i_2_n_6\,
      O(0) => \btn_cnt_reg[1][0]_i_2_n_7\,
      S(3 downto 1) => \btn_cnt_reg[1]_1\(3 downto 1),
      S(0) => \btn_cnt[1][0]_i_3_n_0\
    );
\btn_cnt_reg[1][10]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][8]_i_1_n_5\,
      Q => \btn_cnt_reg[1]_1\(10),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][11]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][8]_i_1_n_4\,
      Q => \btn_cnt_reg[1]_1\(11),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][12]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][12]_i_1_n_7\,
      Q => \btn_cnt_reg[1]_1\(12),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[1][8]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[1][12]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[1][12]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[1][12]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[1][12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[1][12]_i_1_n_4\,
      O(2) => \btn_cnt_reg[1][12]_i_1_n_5\,
      O(1) => \btn_cnt_reg[1][12]_i_1_n_6\,
      O(0) => \btn_cnt_reg[1][12]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[1]_1\(15 downto 12)
    );
\btn_cnt_reg[1][13]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][12]_i_1_n_6\,
      Q => \btn_cnt_reg[1]_1\(13),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][14]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][12]_i_1_n_5\,
      Q => \btn_cnt_reg[1]_1\(14),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][15]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][12]_i_1_n_4\,
      Q => \btn_cnt_reg[1]_1\(15),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][16]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][16]_i_1_n_7\,
      Q => \btn_cnt_reg[1]_1\(16),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[1][12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_btn_cnt_reg[1][16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \btn_cnt_reg[1][16]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[1][16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_btn_cnt_reg[1][16]_i_1_O_UNCONNECTED\(3),
      O(2) => \btn_cnt_reg[1][16]_i_1_n_5\,
      O(1) => \btn_cnt_reg[1][16]_i_1_n_6\,
      O(0) => \btn_cnt_reg[1][16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => \btn_cnt_reg[1]_1\(18 downto 16)
    );
\btn_cnt_reg[1][17]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][16]_i_1_n_6\,
      Q => \btn_cnt_reg[1]_1\(17),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][18]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][16]_i_1_n_5\,
      Q => \btn_cnt_reg[1]_1\(18),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][1]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][0]_i_2_n_6\,
      Q => \btn_cnt_reg[1]_1\(1),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][2]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][0]_i_2_n_5\,
      Q => \btn_cnt_reg[1]_1\(2),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][3]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][0]_i_2_n_4\,
      Q => \btn_cnt_reg[1]_1\(3),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][4]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][4]_i_1_n_7\,
      Q => \btn_cnt_reg[1]_1\(4),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[1][0]_i_2_n_0\,
      CO(3) => \btn_cnt_reg[1][4]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[1][4]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[1][4]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[1][4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[1][4]_i_1_n_4\,
      O(2) => \btn_cnt_reg[1][4]_i_1_n_5\,
      O(1) => \btn_cnt_reg[1][4]_i_1_n_6\,
      O(0) => \btn_cnt_reg[1][4]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[1]_1\(7 downto 4)
    );
\btn_cnt_reg[1][5]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][4]_i_1_n_6\,
      Q => \btn_cnt_reg[1]_1\(5),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][6]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][4]_i_1_n_5\,
      Q => \btn_cnt_reg[1]_1\(6),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][7]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][4]_i_1_n_4\,
      Q => \btn_cnt_reg[1]_1\(7),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][8]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][8]_i_1_n_7\,
      Q => \btn_cnt_reg[1]_1\(8),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[1][8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[1][4]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[1][8]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[1][8]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[1][8]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[1][8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[1][8]_i_1_n_4\,
      O(2) => \btn_cnt_reg[1][8]_i_1_n_5\,
      O(1) => \btn_cnt_reg[1][8]_i_1_n_6\,
      O(0) => \btn_cnt_reg[1][8]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[1]_1\(11 downto 8)
    );
\btn_cnt_reg[1][9]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[1][8]_i_1_n_6\,
      Q => \btn_cnt_reg[1]_1\(9),
      R => \btn_cnt[1][0]_i_1_n_0\
    );
\btn_cnt_reg[2][0]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][0]_i_2_n_7\,
      Q => \btn_cnt_reg[2]_2\(0),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \btn_cnt_reg[2][0]_i_2_n_0\,
      CO(2) => \btn_cnt_reg[2][0]_i_2_n_1\,
      CO(1) => \btn_cnt_reg[2][0]_i_2_n_2\,
      CO(0) => \btn_cnt_reg[2][0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \btn_cnt_reg[2][0]_i_2_n_4\,
      O(2) => \btn_cnt_reg[2][0]_i_2_n_5\,
      O(1) => \btn_cnt_reg[2][0]_i_2_n_6\,
      O(0) => \btn_cnt_reg[2][0]_i_2_n_7\,
      S(3 downto 1) => \btn_cnt_reg[2]_2\(3 downto 1),
      S(0) => \btn_cnt[2][0]_i_3_n_0\
    );
\btn_cnt_reg[2][10]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][8]_i_1_n_5\,
      Q => \btn_cnt_reg[2]_2\(10),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][11]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][8]_i_1_n_4\,
      Q => \btn_cnt_reg[2]_2\(11),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][12]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][12]_i_1_n_7\,
      Q => \btn_cnt_reg[2]_2\(12),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[2][8]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[2][12]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[2][12]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[2][12]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[2][12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[2][12]_i_1_n_4\,
      O(2) => \btn_cnt_reg[2][12]_i_1_n_5\,
      O(1) => \btn_cnt_reg[2][12]_i_1_n_6\,
      O(0) => \btn_cnt_reg[2][12]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[2]_2\(15 downto 12)
    );
\btn_cnt_reg[2][13]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][12]_i_1_n_6\,
      Q => \btn_cnt_reg[2]_2\(13),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][14]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][12]_i_1_n_5\,
      Q => \btn_cnt_reg[2]_2\(14),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][15]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][12]_i_1_n_4\,
      Q => \btn_cnt_reg[2]_2\(15),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][16]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][16]_i_1_n_7\,
      Q => \btn_cnt_reg[2]_2\(16),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[2][12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_btn_cnt_reg[2][16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \btn_cnt_reg[2][16]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[2][16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_btn_cnt_reg[2][16]_i_1_O_UNCONNECTED\(3),
      O(2) => \btn_cnt_reg[2][16]_i_1_n_5\,
      O(1) => \btn_cnt_reg[2][16]_i_1_n_6\,
      O(0) => \btn_cnt_reg[2][16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => \btn_cnt_reg[2]_2\(18 downto 16)
    );
\btn_cnt_reg[2][17]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][16]_i_1_n_6\,
      Q => \btn_cnt_reg[2]_2\(17),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][18]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][16]_i_1_n_5\,
      Q => \btn_cnt_reg[2]_2\(18),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][1]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][0]_i_2_n_6\,
      Q => \btn_cnt_reg[2]_2\(1),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][2]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][0]_i_2_n_5\,
      Q => \btn_cnt_reg[2]_2\(2),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][3]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][0]_i_2_n_4\,
      Q => \btn_cnt_reg[2]_2\(3),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][4]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][4]_i_1_n_7\,
      Q => \btn_cnt_reg[2]_2\(4),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[2][0]_i_2_n_0\,
      CO(3) => \btn_cnt_reg[2][4]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[2][4]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[2][4]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[2][4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[2][4]_i_1_n_4\,
      O(2) => \btn_cnt_reg[2][4]_i_1_n_5\,
      O(1) => \btn_cnt_reg[2][4]_i_1_n_6\,
      O(0) => \btn_cnt_reg[2][4]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[2]_2\(7 downto 4)
    );
\btn_cnt_reg[2][5]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][4]_i_1_n_6\,
      Q => \btn_cnt_reg[2]_2\(5),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][6]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][4]_i_1_n_5\,
      Q => \btn_cnt_reg[2]_2\(6),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][7]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][4]_i_1_n_4\,
      Q => \btn_cnt_reg[2]_2\(7),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][8]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][8]_i_1_n_7\,
      Q => \btn_cnt_reg[2]_2\(8),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[2][8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[2][4]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[2][8]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[2][8]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[2][8]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[2][8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[2][8]_i_1_n_4\,
      O(2) => \btn_cnt_reg[2][8]_i_1_n_5\,
      O(1) => \btn_cnt_reg[2][8]_i_1_n_6\,
      O(0) => \btn_cnt_reg[2][8]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[2]_2\(11 downto 8)
    );
\btn_cnt_reg[2][9]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[2][8]_i_1_n_6\,
      Q => \btn_cnt_reg[2]_2\(9),
      R => \btn_cnt[2][0]_i_1_n_0\
    );
\btn_cnt_reg[3][0]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][0]_i_2_n_7\,
      Q => \btn_cnt_reg[3]_3\(0),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \btn_cnt_reg[3][0]_i_2_n_0\,
      CO(2) => \btn_cnt_reg[3][0]_i_2_n_1\,
      CO(1) => \btn_cnt_reg[3][0]_i_2_n_2\,
      CO(0) => \btn_cnt_reg[3][0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \btn_cnt_reg[3][0]_i_2_n_4\,
      O(2) => \btn_cnt_reg[3][0]_i_2_n_5\,
      O(1) => \btn_cnt_reg[3][0]_i_2_n_6\,
      O(0) => \btn_cnt_reg[3][0]_i_2_n_7\,
      S(3 downto 1) => \btn_cnt_reg[3]_3\(3 downto 1),
      S(0) => \btn_cnt[3][0]_i_3_n_0\
    );
\btn_cnt_reg[3][10]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][8]_i_1_n_5\,
      Q => \btn_cnt_reg[3]_3\(10),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][11]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][8]_i_1_n_4\,
      Q => \btn_cnt_reg[3]_3\(11),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][12]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][12]_i_1_n_7\,
      Q => \btn_cnt_reg[3]_3\(12),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[3][8]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[3][12]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[3][12]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[3][12]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[3][12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[3][12]_i_1_n_4\,
      O(2) => \btn_cnt_reg[3][12]_i_1_n_5\,
      O(1) => \btn_cnt_reg[3][12]_i_1_n_6\,
      O(0) => \btn_cnt_reg[3][12]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[3]_3\(15 downto 12)
    );
\btn_cnt_reg[3][13]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][12]_i_1_n_6\,
      Q => \btn_cnt_reg[3]_3\(13),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][14]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][12]_i_1_n_5\,
      Q => \btn_cnt_reg[3]_3\(14),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][15]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][12]_i_1_n_4\,
      Q => \btn_cnt_reg[3]_3\(15),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][16]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][16]_i_1_n_7\,
      Q => \btn_cnt_reg[3]_3\(16),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[3][12]_i_1_n_0\,
      CO(3 downto 2) => \NLW_btn_cnt_reg[3][16]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \btn_cnt_reg[3][16]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[3][16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_btn_cnt_reg[3][16]_i_1_O_UNCONNECTED\(3),
      O(2) => \btn_cnt_reg[3][16]_i_1_n_5\,
      O(1) => \btn_cnt_reg[3][16]_i_1_n_6\,
      O(0) => \btn_cnt_reg[3][16]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => \btn_cnt_reg[3]_3\(18 downto 16)
    );
\btn_cnt_reg[3][17]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][16]_i_1_n_6\,
      Q => \btn_cnt_reg[3]_3\(17),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][18]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][16]_i_1_n_5\,
      Q => \btn_cnt_reg[3]_3\(18),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][1]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][0]_i_2_n_6\,
      Q => \btn_cnt_reg[3]_3\(1),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][2]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][0]_i_2_n_5\,
      Q => \btn_cnt_reg[3]_3\(2),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][3]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][0]_i_2_n_4\,
      Q => \btn_cnt_reg[3]_3\(3),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][4]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][4]_i_1_n_7\,
      Q => \btn_cnt_reg[3]_3\(4),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[3][0]_i_2_n_0\,
      CO(3) => \btn_cnt_reg[3][4]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[3][4]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[3][4]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[3][4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[3][4]_i_1_n_4\,
      O(2) => \btn_cnt_reg[3][4]_i_1_n_5\,
      O(1) => \btn_cnt_reg[3][4]_i_1_n_6\,
      O(0) => \btn_cnt_reg[3][4]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[3]_3\(7 downto 4)
    );
\btn_cnt_reg[3][5]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][4]_i_1_n_6\,
      Q => \btn_cnt_reg[3]_3\(5),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][6]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][4]_i_1_n_5\,
      Q => \btn_cnt_reg[3]_3\(6),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][7]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][4]_i_1_n_4\,
      Q => \btn_cnt_reg[3]_3\(7),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][8]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][8]_i_1_n_7\,
      Q => \btn_cnt_reg[3]_3\(8),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_cnt_reg[3][8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \btn_cnt_reg[3][4]_i_1_n_0\,
      CO(3) => \btn_cnt_reg[3][8]_i_1_n_0\,
      CO(2) => \btn_cnt_reg[3][8]_i_1_n_1\,
      CO(1) => \btn_cnt_reg[3][8]_i_1_n_2\,
      CO(0) => \btn_cnt_reg[3][8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \btn_cnt_reg[3][8]_i_1_n_4\,
      O(2) => \btn_cnt_reg[3][8]_i_1_n_5\,
      O(1) => \btn_cnt_reg[3][8]_i_1_n_6\,
      O(0) => \btn_cnt_reg[3][8]_i_1_n_7\,
      S(3 downto 0) => \btn_cnt_reg[3]_3\(11 downto 8)
    );
\btn_cnt_reg[3][9]\: unisim.vcomponents.FDRE
     port map (
      C => sys_clk,
      CE => '1',
      D => \btn_cnt_reg[3][8]_i_1_n_6\,
      Q => \btn_cnt_reg[3]_3\(9),
      R => \btn_cnt[3][0]_i_1_n_0\
    );
\btn_complete[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3808"
    )
        port map (
      I0 => \btn_pressed_reg_n_0_[0]\,
      I1 => \btn_stable_reg_n_0_[0]\,
      I2 => \btn_prev_reg_n_0_[0]\,
      I3 => \btn_complete_reg_n_0_[0]\,
      O => \btn_complete[0]_i_1_n_0\
    );
\btn_complete[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3808"
    )
        port map (
      I0 => p_2_in20_in,
      I1 => \btn_stable_reg_n_0_[1]\,
      I2 => p_0_in33_in,
      I3 => \btn_complete_reg_n_0_[1]\,
      O => \btn_complete[1]_i_1_n_0\
    );
\btn_complete[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3808"
    )
        port map (
      I0 => p_2_in24_in,
      I1 => p_0_in1_in,
      I2 => p_0_in36_in,
      I3 => p_0_in,
      O => \btn_complete[2]_i_1_n_0\
    );
\btn_complete[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"3808"
    )
        port map (
      I0 => p_2_in28_in,
      I1 => p_0_in4_in,
      I2 => p_0_in39_in,
      I3 => p_1_in,
      O => \btn_complete[3]_i_1_n_0\
    );
\btn_complete_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_complete[0]_i_1_n_0\,
      Q => \btn_complete_reg_n_0_[0]\,
      R => '0'
    );
\btn_complete_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_complete[1]_i_1_n_0\,
      Q => \btn_complete_reg_n_0_[1]\,
      R => '0'
    );
\btn_complete_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_complete[2]_i_1_n_0\,
      Q => p_0_in,
      R => '0'
    );
\btn_complete_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_complete[3]_i_1_n_0\,
      Q => p_1_in,
      R => '0'
    );
\btn_pressed[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8E"
    )
        port map (
      I0 => \btn_pressed_reg_n_0_[0]\,
      I1 => \btn_prev_reg_n_0_[0]\,
      I2 => \btn_stable_reg_n_0_[0]\,
      O => \btn_pressed[0]_i_1_n_0\
    );
\btn_pressed[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8E"
    )
        port map (
      I0 => p_2_in20_in,
      I1 => p_0_in33_in,
      I2 => \btn_stable_reg_n_0_[1]\,
      O => \btn_pressed[1]_i_1_n_0\
    );
\btn_pressed[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8E"
    )
        port map (
      I0 => p_2_in24_in,
      I1 => p_0_in36_in,
      I2 => p_0_in1_in,
      O => \btn_pressed[2]_i_1_n_0\
    );
\btn_pressed[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8E"
    )
        port map (
      I0 => p_2_in28_in,
      I1 => p_0_in39_in,
      I2 => p_0_in4_in,
      O => \btn_pressed[3]_i_1_n_0\
    );
\btn_pressed_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_pressed[0]_i_1_n_0\,
      Q => \btn_pressed_reg_n_0_[0]\,
      R => '0'
    );
\btn_pressed_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_pressed[1]_i_1_n_0\,
      Q => p_2_in20_in,
      R => '0'
    );
\btn_pressed_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_pressed[2]_i_1_n_0\,
      Q => p_2_in24_in,
      R => '0'
    );
\btn_pressed_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_pressed[3]_i_1_n_0\,
      Q => p_2_in28_in,
      R => '0'
    );
\btn_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_stable_reg_n_0_[0]\,
      Q => \btn_prev_reg_n_0_[0]\,
      R => '0'
    );
\btn_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_stable_reg_n_0_[1]\,
      Q => p_0_in33_in,
      R => '0'
    );
\btn_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => p_0_in1_in,
      Q => p_0_in36_in,
      R => '0'
    );
\btn_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => p_0_in4_in,
      Q => p_0_in39_in,
      R => '0'
    );
\btn_stable[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAACCCCCCCCCCC"
    )
        port map (
      I0 => btn(0),
      I1 => \btn_stable_reg_n_0_[0]\,
      I2 => \btn_stable[0]_i_2_n_0\,
      I3 => \btn_cnt_reg[0]_0\(13),
      I4 => \btn_cnt_reg[0]_0\(14),
      I5 => \btn_stable[0]_i_3_n_0\,
      O => \btn_stable[0]_i_1_n_0\
    );
\btn_stable[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => \btn_cnt_reg[0]_0\(8),
      I1 => \btn_stable[0]_i_4_n_0\,
      I2 => \btn_stable[0]_i_5_n_0\,
      I3 => \btn_cnt_reg[0]_0\(10),
      I4 => \btn_cnt_reg[0]_0\(11),
      I5 => \btn_stable[0]_i_6_n_0\,
      O => \btn_stable[0]_i_2_n_0\
    );
\btn_stable[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \btn_cnt_reg[0]_0\(16),
      I1 => \btn_cnt_reg[0]_0\(15),
      I2 => \btn_cnt_reg[0]_0\(18),
      I3 => \btn_cnt_reg[0]_0\(17),
      O => \btn_stable[0]_i_3_n_0\
    );
\btn_stable[0]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \btn_cnt_reg[0]_0\(0),
      I1 => \btn_cnt_reg[0]_0\(1),
      I2 => \btn_cnt_reg[0]_0\(2),
      I3 => \btn_cnt_reg[0]_0\(4),
      I4 => \btn_cnt_reg[0]_0\(3),
      O => \btn_stable[0]_i_4_n_0\
    );
\btn_stable[0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \btn_cnt_reg[0]_0\(6),
      I1 => \btn_cnt_reg[0]_0\(5),
      I2 => \btn_cnt_reg[0]_0\(7),
      O => \btn_stable[0]_i_5_n_0\
    );
\btn_stable[0]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \btn_cnt_reg[0]_0\(9),
      I1 => \btn_cnt_reg[0]_0\(12),
      O => \btn_stable[0]_i_6_n_0\
    );
\btn_stable[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAACCCCCCCCCCC"
    )
        port map (
      I0 => btn(1),
      I1 => \btn_stable_reg_n_0_[1]\,
      I2 => \btn_stable[1]_i_2_n_0\,
      I3 => \btn_cnt_reg[1]_1\(13),
      I4 => \btn_cnt_reg[1]_1\(14),
      I5 => \btn_stable[1]_i_3_n_0\,
      O => \btn_stable[1]_i_1_n_0\
    );
\btn_stable[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => \btn_cnt_reg[1]_1\(8),
      I1 => \btn_stable[1]_i_4_n_0\,
      I2 => \btn_stable[1]_i_5_n_0\,
      I3 => \btn_cnt_reg[1]_1\(10),
      I4 => \btn_cnt_reg[1]_1\(11),
      I5 => \btn_stable[1]_i_6_n_0\,
      O => \btn_stable[1]_i_2_n_0\
    );
\btn_stable[1]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \btn_cnt_reg[1]_1\(16),
      I1 => \btn_cnt_reg[1]_1\(15),
      I2 => \btn_cnt_reg[1]_1\(18),
      I3 => \btn_cnt_reg[1]_1\(17),
      O => \btn_stable[1]_i_3_n_0\
    );
\btn_stable[1]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \btn_cnt_reg[1]_1\(0),
      I1 => \btn_cnt_reg[1]_1\(1),
      I2 => \btn_cnt_reg[1]_1\(2),
      I3 => \btn_cnt_reg[1]_1\(4),
      I4 => \btn_cnt_reg[1]_1\(3),
      O => \btn_stable[1]_i_4_n_0\
    );
\btn_stable[1]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \btn_cnt_reg[1]_1\(6),
      I1 => \btn_cnt_reg[1]_1\(5),
      I2 => \btn_cnt_reg[1]_1\(7),
      O => \btn_stable[1]_i_5_n_0\
    );
\btn_stable[1]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \btn_cnt_reg[1]_1\(9),
      I1 => \btn_cnt_reg[1]_1\(12),
      O => \btn_stable[1]_i_6_n_0\
    );
\btn_stable[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAACCCCCCCCCCC"
    )
        port map (
      I0 => btn(2),
      I1 => p_0_in1_in,
      I2 => \btn_stable[2]_i_2_n_0\,
      I3 => \btn_cnt_reg[2]_2\(13),
      I4 => \btn_cnt_reg[2]_2\(14),
      I5 => \btn_stable[2]_i_3_n_0\,
      O => \btn_stable[2]_i_1_n_0\
    );
\btn_stable[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => \btn_cnt_reg[2]_2\(8),
      I1 => \btn_stable[2]_i_4_n_0\,
      I2 => \btn_stable[2]_i_5_n_0\,
      I3 => \btn_cnt_reg[2]_2\(10),
      I4 => \btn_cnt_reg[2]_2\(11),
      I5 => \btn_stable[2]_i_6_n_0\,
      O => \btn_stable[2]_i_2_n_0\
    );
\btn_stable[2]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \btn_cnt_reg[2]_2\(16),
      I1 => \btn_cnt_reg[2]_2\(15),
      I2 => \btn_cnt_reg[2]_2\(18),
      I3 => \btn_cnt_reg[2]_2\(17),
      O => \btn_stable[2]_i_3_n_0\
    );
\btn_stable[2]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \btn_cnt_reg[2]_2\(0),
      I1 => \btn_cnt_reg[2]_2\(1),
      I2 => \btn_cnt_reg[2]_2\(2),
      I3 => \btn_cnt_reg[2]_2\(4),
      I4 => \btn_cnt_reg[2]_2\(3),
      O => \btn_stable[2]_i_4_n_0\
    );
\btn_stable[2]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \btn_cnt_reg[2]_2\(6),
      I1 => \btn_cnt_reg[2]_2\(5),
      I2 => \btn_cnt_reg[2]_2\(7),
      O => \btn_stable[2]_i_5_n_0\
    );
\btn_stable[2]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \btn_cnt_reg[2]_2\(9),
      I1 => \btn_cnt_reg[2]_2\(12),
      O => \btn_stable[2]_i_6_n_0\
    );
\btn_stable[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAACCCCCCCCCCC"
    )
        port map (
      I0 => btn(3),
      I1 => p_0_in4_in,
      I2 => \btn_stable[3]_i_2_n_0\,
      I3 => \btn_cnt_reg[3]_3\(13),
      I4 => \btn_cnt_reg[3]_3\(14),
      I5 => \btn_stable[3]_i_3_n_0\,
      O => \btn_stable[3]_i_1_n_0\
    );
\btn_stable[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFA8"
    )
        port map (
      I0 => \btn_cnt_reg[3]_3\(8),
      I1 => \btn_stable[3]_i_4_n_0\,
      I2 => \btn_stable[3]_i_5_n_0\,
      I3 => \btn_cnt_reg[3]_3\(10),
      I4 => \btn_cnt_reg[3]_3\(11),
      I5 => \btn_stable[3]_i_6_n_0\,
      O => \btn_stable[3]_i_2_n_0\
    );
\btn_stable[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \btn_cnt_reg[3]_3\(16),
      I1 => \btn_cnt_reg[3]_3\(15),
      I2 => \btn_cnt_reg[3]_3\(18),
      I3 => \btn_cnt_reg[3]_3\(17),
      O => \btn_stable[3]_i_3_n_0\
    );
\btn_stable[3]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \btn_cnt_reg[3]_3\(0),
      I1 => \btn_cnt_reg[3]_3\(1),
      I2 => \btn_cnt_reg[3]_3\(2),
      I3 => \btn_cnt_reg[3]_3\(4),
      I4 => \btn_cnt_reg[3]_3\(3),
      O => \btn_stable[3]_i_4_n_0\
    );
\btn_stable[3]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \btn_cnt_reg[3]_3\(6),
      I1 => \btn_cnt_reg[3]_3\(5),
      I2 => \btn_cnt_reg[3]_3\(7),
      O => \btn_stable[3]_i_5_n_0\
    );
\btn_stable[3]_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \btn_cnt_reg[3]_3\(9),
      I1 => \btn_cnt_reg[3]_3\(12),
      O => \btn_stable[3]_i_6_n_0\
    );
\btn_stable_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_stable[0]_i_1_n_0\,
      Q => \btn_stable_reg_n_0_[0]\,
      R => '0'
    );
\btn_stable_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_stable[1]_i_1_n_0\,
      Q => \btn_stable_reg_n_0_[1]\,
      R => '0'
    );
\btn_stable_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_stable[2]_i_1_n_0\,
      Q => p_0_in1_in,
      R => '0'
    );
\btn_stable_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \btn_stable[3]_i_1_n_0\,
      Q => p_0_in4_in,
      R => '0'
    );
\color_idx[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"15AA"
    )
        port map (
      I0 => \color_idx_reg_n_0_[0]\,
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => sec_pulse,
      O => \color_idx[0]_i_1_n_0\
    );
\color_idx[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1AF0"
    )
        port map (
      I0 => \color_idx_reg_n_0_[0]\,
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => sec_pulse,
      O => \color_idx[1]_i_1_n_0\
    );
\color_idx[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2CCC"
    )
        port map (
      I0 => \color_idx_reg_n_0_[0]\,
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => sec_pulse,
      O => \color_idx[2]_i_1_n_0\
    );
\color_idx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \color_idx[0]_i_1_n_0\,
      Q => \color_idx_reg_n_0_[0]\,
      R => '0'
    );
\color_idx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \color_idx[1]_i_1_n_0\,
      Q => \color_idx_reg_n_0_[1]\,
      R => '0'
    );
\color_idx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \color_idx[2]_i_1_n_0\,
      Q => \color_idx_reg_n_0_[2]\,
      R => '0'
    );
\led[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B833"
    )
        port map (
      I0 => blink_reg(0),
      I1 => \led_mode_reg_n_0_[0]\,
      I2 => shift_reg(0),
      I3 => \led_mode_reg_n_0_[1]\,
      O => led(0)
    );
\led[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B833"
    )
        port map (
      I0 => blink_reg(1),
      I1 => \led_mode_reg_n_0_[0]\,
      I2 => shift_reg(1),
      I3 => \led_mode_reg_n_0_[1]\,
      O => led(1)
    );
\led[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B833"
    )
        port map (
      I0 => blink_reg(2),
      I1 => \led_mode_reg_n_0_[0]\,
      I2 => shift_reg(2),
      I3 => \led_mode_reg_n_0_[1]\,
      O => led(2)
    );
\led[3]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B833"
    )
        port map (
      I0 => blink_reg(3),
      I1 => \led_mode_reg_n_0_[0]\,
      I2 => shift_reg(3),
      I3 => \led_mode_reg_n_0_[1]\,
      O => led(3)
    );
\led_mode[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"55115510"
    )
        port map (
      I0 => \btn_complete_reg_n_0_[0]\,
      I1 => p_0_in,
      I2 => p_1_in,
      I3 => \btn_complete_reg_n_0_[1]\,
      I4 => \led_mode_reg_n_0_[0]\,
      O => \led_mode[0]_i_1_n_0\
    );
\led_mode[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00550054"
    )
        port map (
      I0 => \btn_complete_reg_n_0_[0]\,
      I1 => p_0_in,
      I2 => p_1_in,
      I3 => \btn_complete_reg_n_0_[1]\,
      I4 => \led_mode_reg_n_0_[1]\,
      O => \led_mode[1]_i_1_n_0\
    );
\led_mode_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \led_mode[0]_i_1_n_0\,
      Q => \led_mode_reg_n_0_[0]\,
      R => '0'
    );
\led_mode_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \led_mode[1]_i_1_n_0\,
      Q => \led_mode_reg_n_0_[1]\,
      R => '0'
    );
\rgbled0[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"20A8"
    )
        port map (
      I0 => sw(0),
      I1 => \color_idx_reg_n_0_[1]\,
      I2 => \color_idx_reg_n_0_[2]\,
      I3 => \color_idx_reg_n_0_[0]\,
      O => rgbled0(0)
    );
\rgbled0[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => sw(0),
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => \color_idx_reg_n_0_[0]\,
      O => rgbled0(1)
    );
\rgbled0[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"208A"
    )
        port map (
      I0 => sw(0),
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => \color_idx_reg_n_0_[0]\,
      O => rgbled0(2)
    );
\rgbled1[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"20A8"
    )
        port map (
      I0 => sw(1),
      I1 => \color_idx_reg_n_0_[1]\,
      I2 => \color_idx_reg_n_0_[2]\,
      I3 => \color_idx_reg_n_0_[0]\,
      O => rgbled1(0)
    );
\rgbled1[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2A80"
    )
        port map (
      I0 => sw(1),
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => \color_idx_reg_n_0_[0]\,
      O => rgbled1(1)
    );
\rgbled1[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"208A"
    )
        port map (
      I0 => sw(1),
      I1 => \color_idx_reg_n_0_[2]\,
      I2 => \color_idx_reg_n_0_[1]\,
      I3 => \color_idx_reg_n_0_[0]\,
      O => rgbled1(2)
    );
sec_pulse_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A8A8A8A8A8888888"
    )
        port map (
      I0 => sec_pulse_i_2_n_0,
      I1 => time_cnt_reg(23),
      I2 => sec_pulse_i_3_n_0,
      I3 => sec_pulse_i_4_n_0,
      I4 => sec_pulse_i_5_n_0,
      I5 => sec_pulse_i_6_n_0,
      O => sec_pulse_i_1_n_0
    );
sec_pulse_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => time_cnt_reg(2),
      I1 => time_cnt_reg(3),
      I2 => time_cnt_reg(0),
      I3 => time_cnt_reg(1),
      I4 => time_cnt_reg(5),
      I5 => time_cnt_reg(4),
      O => sec_pulse_i_10_n_0
    );
sec_pulse_i_11: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => time_cnt_reg(12),
      I1 => time_cnt_reg(11),
      I2 => time_cnt_reg(14),
      O => sec_pulse_i_11_n_0
    );
sec_pulse_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => time_cnt_reg(26),
      I1 => time_cnt_reg(25),
      I2 => time_cnt_reg(24),
      O => sec_pulse_i_2_n_0
    );
sec_pulse_i_3: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => time_cnt_reg(22),
      I1 => time_cnt_reg(21),
      I2 => time_cnt_reg(20),
      O => sec_pulse_i_3_n_0
    );
sec_pulse_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => time_cnt_reg(16),
      I1 => time_cnt_reg(17),
      O => sec_pulse_i_4_n_0
    );
sec_pulse_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEEEEEAAAAAAAA"
    )
        port map (
      I0 => sec_pulse_i_7_n_0,
      I1 => sec_pulse_i_8_n_0,
      I2 => sec_pulse_i_9_n_0,
      I3 => sec_pulse_i_10_n_0,
      I4 => time_cnt_reg(8),
      I5 => sec_pulse_i_11_n_0,
      O => sec_pulse_i_5_n_0
    );
sec_pulse_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_cnt_reg(18),
      I1 => time_cnt_reg(19),
      O => sec_pulse_i_6_n_0
    );
sec_pulse_i_7: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => time_cnt_reg(13),
      I1 => time_cnt_reg(14),
      I2 => time_cnt_reg(15),
      O => sec_pulse_i_7_n_0
    );
sec_pulse_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_cnt_reg(9),
      I1 => time_cnt_reg(10),
      O => sec_pulse_i_8_n_0
    );
sec_pulse_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => time_cnt_reg(6),
      I1 => time_cnt_reg(7),
      O => sec_pulse_i_9_n_0
    );
sec_pulse_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => sec_pulse_i_1_n_0,
      Q => sec_pulse,
      R => '0'
    );
shift_reg0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => sec_pulse,
      I1 => \led_mode_reg_n_0_[0]\,
      I2 => \led_mode_reg_n_0_[1]\,
      O => \shift_reg0__0\
    );
\shift_reg_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => sys_clk,
      CE => \shift_reg0__0\,
      D => shift_reg(3),
      Q => shift_reg(0),
      S => p_0_in
    );
\shift_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => \shift_reg0__0\,
      D => shift_reg(0),
      Q => shift_reg(1),
      R => p_0_in
    );
\shift_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => \shift_reg0__0\,
      D => shift_reg(1),
      Q => shift_reg(2),
      R => p_0_in
    );
\shift_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => \shift_reg0__0\,
      D => shift_reg(2),
      Q => shift_reg(3),
      R => p_0_in
    );
\time_cnt[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => time_cnt_reg(0),
      O => \time_cnt[0]_i_2_n_0\
    );
\time_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[0]_i_1_n_7\,
      Q => time_cnt_reg(0),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \time_cnt_reg[0]_i_1_n_0\,
      CO(2) => \time_cnt_reg[0]_i_1_n_1\,
      CO(1) => \time_cnt_reg[0]_i_1_n_2\,
      CO(0) => \time_cnt_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \time_cnt_reg[0]_i_1_n_4\,
      O(2) => \time_cnt_reg[0]_i_1_n_5\,
      O(1) => \time_cnt_reg[0]_i_1_n_6\,
      O(0) => \time_cnt_reg[0]_i_1_n_7\,
      S(3 downto 1) => time_cnt_reg(3 downto 1),
      S(0) => \time_cnt[0]_i_2_n_0\
    );
\time_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[8]_i_1_n_5\,
      Q => time_cnt_reg(10),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[8]_i_1_n_4\,
      Q => time_cnt_reg(11),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[12]_i_1_n_7\,
      Q => time_cnt_reg(12),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_cnt_reg[8]_i_1_n_0\,
      CO(3) => \time_cnt_reg[12]_i_1_n_0\,
      CO(2) => \time_cnt_reg[12]_i_1_n_1\,
      CO(1) => \time_cnt_reg[12]_i_1_n_2\,
      CO(0) => \time_cnt_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_cnt_reg[12]_i_1_n_4\,
      O(2) => \time_cnt_reg[12]_i_1_n_5\,
      O(1) => \time_cnt_reg[12]_i_1_n_6\,
      O(0) => \time_cnt_reg[12]_i_1_n_7\,
      S(3 downto 0) => time_cnt_reg(15 downto 12)
    );
\time_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[12]_i_1_n_6\,
      Q => time_cnt_reg(13),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[12]_i_1_n_5\,
      Q => time_cnt_reg(14),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[12]_i_1_n_4\,
      Q => time_cnt_reg(15),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[16]_i_1_n_7\,
      Q => time_cnt_reg(16),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_cnt_reg[12]_i_1_n_0\,
      CO(3) => \time_cnt_reg[16]_i_1_n_0\,
      CO(2) => \time_cnt_reg[16]_i_1_n_1\,
      CO(1) => \time_cnt_reg[16]_i_1_n_2\,
      CO(0) => \time_cnt_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_cnt_reg[16]_i_1_n_4\,
      O(2) => \time_cnt_reg[16]_i_1_n_5\,
      O(1) => \time_cnt_reg[16]_i_1_n_6\,
      O(0) => \time_cnt_reg[16]_i_1_n_7\,
      S(3 downto 0) => time_cnt_reg(19 downto 16)
    );
\time_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[16]_i_1_n_6\,
      Q => time_cnt_reg(17),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[16]_i_1_n_5\,
      Q => time_cnt_reg(18),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[16]_i_1_n_4\,
      Q => time_cnt_reg(19),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[0]_i_1_n_6\,
      Q => time_cnt_reg(1),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[20]_i_1_n_7\,
      Q => time_cnt_reg(20),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_cnt_reg[16]_i_1_n_0\,
      CO(3) => \time_cnt_reg[20]_i_1_n_0\,
      CO(2) => \time_cnt_reg[20]_i_1_n_1\,
      CO(1) => \time_cnt_reg[20]_i_1_n_2\,
      CO(0) => \time_cnt_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_cnt_reg[20]_i_1_n_4\,
      O(2) => \time_cnt_reg[20]_i_1_n_5\,
      O(1) => \time_cnt_reg[20]_i_1_n_6\,
      O(0) => \time_cnt_reg[20]_i_1_n_7\,
      S(3 downto 0) => time_cnt_reg(23 downto 20)
    );
\time_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[20]_i_1_n_6\,
      Q => time_cnt_reg(21),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[20]_i_1_n_5\,
      Q => time_cnt_reg(22),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[20]_i_1_n_4\,
      Q => time_cnt_reg(23),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[24]_i_1_n_7\,
      Q => time_cnt_reg(24),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_cnt_reg[20]_i_1_n_0\,
      CO(3 downto 2) => \NLW_time_cnt_reg[24]_i_1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \time_cnt_reg[24]_i_1_n_2\,
      CO(0) => \time_cnt_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_time_cnt_reg[24]_i_1_O_UNCONNECTED\(3),
      O(2) => \time_cnt_reg[24]_i_1_n_5\,
      O(1) => \time_cnt_reg[24]_i_1_n_6\,
      O(0) => \time_cnt_reg[24]_i_1_n_7\,
      S(3) => '0',
      S(2 downto 0) => time_cnt_reg(26 downto 24)
    );
\time_cnt_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[24]_i_1_n_6\,
      Q => time_cnt_reg(25),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[24]_i_1_n_5\,
      Q => time_cnt_reg(26),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[0]_i_1_n_5\,
      Q => time_cnt_reg(2),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[0]_i_1_n_4\,
      Q => time_cnt_reg(3),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[4]_i_1_n_7\,
      Q => time_cnt_reg(4),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_cnt_reg[0]_i_1_n_0\,
      CO(3) => \time_cnt_reg[4]_i_1_n_0\,
      CO(2) => \time_cnt_reg[4]_i_1_n_1\,
      CO(1) => \time_cnt_reg[4]_i_1_n_2\,
      CO(0) => \time_cnt_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_cnt_reg[4]_i_1_n_4\,
      O(2) => \time_cnt_reg[4]_i_1_n_5\,
      O(1) => \time_cnt_reg[4]_i_1_n_6\,
      O(0) => \time_cnt_reg[4]_i_1_n_7\,
      S(3 downto 0) => time_cnt_reg(7 downto 4)
    );
\time_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[4]_i_1_n_6\,
      Q => time_cnt_reg(5),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[4]_i_1_n_5\,
      Q => time_cnt_reg(6),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[4]_i_1_n_4\,
      Q => time_cnt_reg(7),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[8]_i_1_n_7\,
      Q => time_cnt_reg(8),
      R => sec_pulse_i_1_n_0
    );
\time_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \time_cnt_reg[4]_i_1_n_0\,
      CO(3) => \time_cnt_reg[8]_i_1_n_0\,
      CO(2) => \time_cnt_reg[8]_i_1_n_1\,
      CO(1) => \time_cnt_reg[8]_i_1_n_2\,
      CO(0) => \time_cnt_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \time_cnt_reg[8]_i_1_n_4\,
      O(2) => \time_cnt_reg[8]_i_1_n_5\,
      O(1) => \time_cnt_reg[8]_i_1_n_6\,
      O(0) => \time_cnt_reg[8]_i_1_n_7\,
      S(3 downto 0) => time_cnt_reg(11 downto 8)
    );
\time_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => sys_clk,
      CE => '1',
      D => \time_cnt_reg[8]_i_1_n_6\,
      Q => time_cnt_reg(9),
      R => sec_pulse_i_1_n_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity linux_board_board_test_0_0 is
  port (
    sys_clk : in STD_LOGIC;
    btn : in STD_LOGIC_VECTOR ( 3 downto 0 );
    sw : in STD_LOGIC_VECTOR ( 1 downto 0 );
    led : out STD_LOGIC_VECTOR ( 3 downto 0 );
    rgbled0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rgbled1 : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of linux_board_board_test_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of linux_board_board_test_0_0 : entity is "linux_board_board_test_0_0,board_test,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of linux_board_board_test_0_0 : entity is "yes";
  attribute IP_DEFINITION_SOURCE : string;
  attribute IP_DEFINITION_SOURCE of linux_board_board_test_0_0 : entity is "module_ref";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of linux_board_board_test_0_0 : entity is "board_test,Vivado 2025.1";
end linux_board_board_test_0_0;

architecture STRUCTURE of linux_board_board_test_0_0 is
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of sys_clk : signal is "xilinx.com:signal:clock:1.0 sys_clk CLK";
  attribute X_INTERFACE_MODE : string;
  attribute X_INTERFACE_MODE of sys_clk : signal is "slave";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of sys_clk : signal is "XIL_INTERFACENAME sys_clk, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
begin
inst: entity work.linux_board_board_test_0_0_board_test
     port map (
      btn(3 downto 0) => btn(3 downto 0),
      led(3 downto 0) => led(3 downto 0),
      rgbled0(2 downto 0) => rgbled0(2 downto 0),
      rgbled1(2 downto 0) => rgbled1(2 downto 0),
      sw(1 downto 0) => sw(1 downto 0),
      sys_clk => sys_clk
    );
end STRUCTURE;
